The Internet is a global system of interconnected computer networks that use the standard Internet Protocol Suite (TCP/IP), including Transmission Control Protocol (TCP) and the Internet Protocol (IP), to serve billions of users worldwide. It is a network of networks that consists of millions of private, public, academic, business, and government networks, of local to global scope, that are linked by a broad array of electronic and optical networking technologies. The Internet carries a vast range of information resources and services, such as the interlinked hypertext documents on the World Wide Web (WWW) and the infrastructure to support electronic mail. The Internet backbone refers to the principal data routes between large, strategically interconnected networks and core routers in the Internet. These data routes are hosted by commercial, government, academic and other high-capacity network centers, the Internet exchange points and network access points that interchange Internet traffic between the countries, continents and across the oceans of the world. Traffic interchange between Internet service providers (often Tier 1 networks) participating in the Internet backbone exchange traffic by privately negotiated interconnection agreements, primarily governed by the principle of settlement-free peering.
The Internet, and consequently its backbone networks, does not rely on central control or coordinating facilities, nor do they implement any global network policies. The resilience of the Internet results from its principal architectural features, most notably the idea of placing as few network states and control functions as possible in the network elements, but instead relying on the endpoints of communication to handle most of the processing to ensure data integrity, reliability and authentication. In addition, the high degree of redundancy of today's network links and sophisticated real-time routing protocols provides alternative paths of communications for load balancing and congestion avoidance.
The Internet Protocol (IP) is the principal communications protocol used for relaying datagrams (packets) across an internetwork using the Internet Protocol Suite. Responsible for routing packets across network boundaries, it is the primary protocol that establishes the Internet. IP is the primary protocol in the Internet Layer of the Internet Protocol Suite and has the task of delivering datagrams from the source host to the destination host based on their addresses. For this purpose, IP defines addressing methods and structures for datagram encapsulation. Internet Protocol Version 4 (IPv4) is the dominant protocol of the Internet. IPv4 is described in Internet Engineering Task Force (IETF) Request for Comments (RFC) 791 and RFC 1349, and the successor, Internet Protocol Version 6 (IPv6), is in active and growing deployment worldwide. IPv4 uses 32-bit addresses (providing 4 billion, or 4.3×109 addresses), while IPv6 uses 128-bit addresses (providing 340 undecillion or 3.4×1038 addresses), as described in RFC 2460.
The Internet Protocol is responsible for addressing hosts and routing datagrams (packets) from a source host to the destination host across one or more IP networks. For this purpose the Internet Protocol defines an addressing system that has two functions. Addresses identify hosts and provide a logical location service. Each packet is tagged with a header that contains the meta-data for the purpose of delivery. This process of tagging is also called encapsulation. IP is a connectionless protocol for use in a packet-switched Link Layer network, and does not need circuit setup prior to transmission. The aspects of delivery guaranteeing, proper sequencing, avoidance of duplicate delivery, and data integrity are addressed by an upper transport layer protocol (e.g., TCP—Transmission Control Protocol and UDP—User Datagram Protocol).
The design principles of the Internet protocols assume that the network infrastructure is inherently unreliable at any single network element or transmission medium and that it is dynamic in terms of availability of links and nodes. No central monitoring or performance measurement facility exists that tracks or maintains the state of the entire network. For the benefit of reducing network complexity, end-to-end principle is used, where the intelligence in the network is purposely mostly located at the end nodes of each data transmission. Routers in the transmission path simply forward packets to the next known local gateway, matching the routing prefix for the destination address.
The main aspects of the IP technology are IP addressing and routing. Addressing refers to how end hosts become assigned IP addresses and how sub-networks of IP host addresses are divided and grouped together. IP routing is performed by all hosts, but most importantly by internetwork routers, which typically use either Interior Gateway Protocols (IGPs) or External Gateway Protocols (EGPs) to help make IP datagram forwarding decisions across IP connected networks. Core routers serving in the Internet backbone commonly use the Border Gateway Protocol (BGP) as per RFC 4098 or Multi-Protocol Label Switching (MPLS). Other prior art publications relating to Internet related protocols and routing include the following chapters of the publication number 1-587005-001-3 by Cisco Systems, Inc. (7/99) titled: “Internetworking Technologies Handbook”, which are all incorporated in their entirety for all purposes as if fully set forth herein: Chapter 5: “Routing Basics” (pages 5-1 to 5-10), Chapter 30: “Internet Protocols” (pages 30-1 to 30-16), Chapter 32: “IPv6” (pages 32-1 to 32-6), Chapter 45: “OSI Routing” (pages 45-1 to 45-8) and Chapter 51: “Security” (pages 51-1 to 51-12), as well as IBM Corporation, International Technical Support Organization Redbook Documents No. GG24-4756-00 titled: “Local area Network Concepts and Products: LAN Operation Systems and management”, 1st Edition May 1996, Redbook Document No. GG24-4338-00 titled: “Introduction to Networking Technologies”, 1St Edition April 1994, Redbook Document No. GG24-2580-01 “IP Network Design Guide”, 2nd Edition June 1999, and Redbook Document No. GG24-3376-07 “TCP/IP Tutorial and Technical Overview”, ISBN 0738494682 8th Edition December 2006, which are incorporated in their entirety for all purposes as if fully set forth herein.
A Wireless Mesh Network (WMN) and Wireless Distribution Systems (WDS) are known in the art to be a communication network made up of clients, mesh routers and gateways organized in a mesh topology and connected using radio. Such wireless networks may be based on DSR as the routing protocol. WMNs are standardized in IEEE 802.11s and described in a slide-show by W. Steven Conner, Intel Corp. et al. titled: “IEEE 802.11s Tutorial” presented at the IEEE 802 Plenary, Dallas on Nov. 13, 2006, in a slide-show by Eugen Borcoci of University Politehnica Bucharest, titled: “Wireless Mesh Networks Technologies: Architectures, Protocols, Resource Management and Applications”, presented in INFOWARE Conference on Aug. 22-29, 2009 in Cannes, France, and in an IEEE Communication magazine paper by Joseph D. Camp and Edward W. Knightly of Electrical and Computer Engineering, Rice University, Houston, Tex., USA, titled: “The IEEE 802.11s Extended Service Set Mesh Networking Standard”, which are incorporated in their entirety for all purposes as if fully set forth herein. The arrangement described herein can be equally applied to such wireless networks, wherein two clients exchange information using different paths by using mesh routers as intermediate and relay servers. Commonly in wireless networks, the routing is based on MAC addresses. Hence, the above discussion relating to IP addresses applies in such networks to using the MAC addresses for identifying the client originating the message, the mesh routers (or gateways) serving as the relay servers, and the client serving as the ultimate destination computer.
A schematic view of a prior art internet-based network 10 is shown in FIG. 1a. The Internet or the Internet backbone is shown as the dashed line defining the cloud 11. Various endpoint devices (‘hosts’) such as servers 14a, 14b, 14c, and 14d, laptops 12a and 12b, and desktop computers 13a, 13b, and 13c are shown interconnected via the Internet 11. The Internet backbone 11 contains routers 15a-j interconnected by various bi-directional packet-based communication links 16a-n. The communication link 16a connects routers 15h and 15j, communication link 16b connects routers 15f and 15j, communication link 16c connects routers 15f and 15i, communication link 16d connects routers 15h and 15g, communication link 16e connects routers 15g and 15c, communication link 16f connects routers 15c and 15f, communication link 16g connects routers 15i and 15j, communication link 16h connects routers 15d and 15i, communication link 16i connects routers 15d and 15e, communication link 16k connects routers 15e and 15f, communication link 16l connects routers 15e and 15a, communication link 16m connects routers 15c and 15a, and communication link 16n connects routers 15a and 15b. Similarly, communication link 17a connects laptop 12b to the Internet 11 via router 15a, communication link 17b connects server 14a to router 15a, communication link 17c connects desktop computer 13c to router 15d, communication link 17d connects server 14d to router 15i, communication link 17e connects computer 13b to router 15i, communication link 17f connects server 14b to router 15j, communication link 17g connects laptop 12a to router 15j, communication link 17h connects server 14c to router 15g, and communication link 17i connects computer 13a to router 15c. 
An overview of an IP-based packet 18 is shown in FIG. 1b. The packet may be generally segmented into the IP data 19b to be carried as payload, and the IP header 19f. The IP header 19f contains the IP address of the source as Source IP Address field 19d and the Destination IP Address field 19c. In most cases, the IP header 19f and the payload 19b are further encapsulated by adding a Frame Header 19e and Frame Footer 19a used by higher layer protocols.
The Internet is a packet switching network, wherein packets are forwarded from their source to their ultimate destination via the routers. In one non-limiting example shown as system 20 in FIG. 2, when laptop 12a (‘source’) wishes to send information to desktop computer 13c (‘destination’), a packet is formed at the source, which includes the destination IP address and the source IP address. The packets are routed in the Internet based on various policies and routing algorithms. For example, the packet is first sent to the router 15j over link 17g, as schematically shown by the dashed line path 21a. From router 15j the packet is forwarded to router 15h over link 16a (designated as path 21b), which in turn sends the packet to router 15g over link 16d (path 21c). From router 15g the packet is forwarded to router 15c over link 16e (designated as path 21d), which in turn sends the packet to router 15f over link 16f (path 21e). From router 15f the packet is forwarded to router 15e over link 16k (designated as path 21f), which in turn sends the packet to router 15d over link 16i (path 21g). The packet is then terminated at the destination 13c via link 17c (path 21h).
The Internet structure is using a client-server model, among other models. The terms ‘server’ or ‘server computer’ relates herein to a device or computer (or a series of computers) connected to the Internet and is used for providing specific facilities or services to other computers or other devices (referred to in this context as ‘clients’) connected to the Internet. A server is commonly a host that has an IP address and executes a ‘server program’, and typically operating as a socket listener. Many servers have dedicated functionality such as web server, Domain Name System (DNS) server (described in RFC 1034 and RFC 1035), Dynamic Host Configuration Protocol (DHCP) server (described in RFC 2131 and RFC 3315), mail server, File Transfer Protocol (FTP) server and database server. Similarly, the term ‘client’ herein refers to a program or to a device or a computer (or a series of computers) executing this program, which accesses a server over the Internet for a service or a resource. Clients commonly initiate connections that a server may accept. For example, web browsers are clients that connect to web servers for retrieving web pages, and email clients connect to mail storage servers for retrieving mails.
A network routing is commonly used in the Internet, where the knowledge of the network layout is in the network routing devices, which accordingly determine where to forward the packet. In such a case, the source needs only to specify the destination IP address. Source routing is a method described in RFC 1940 that can be used to specify the route that a packet should take through the network. In source routing the path through the Internet is set by the source. When the sender determines the exact network route the packets must take, ‘strict’ source routing is used. An alternate common form of source routing is called Loose Source Record Route (LSRR). When using the LSRR the sender provides one or more hops (such as an intermediate router) that the packet must go through. The Dynamic Source Routing (DSR) is a simple and efficient on-demand routing protocol designed for use in multi-hop wireless ad hoc network of mobile devices, such as wireless mesh networks. The DSR is described in RFC 4728 and is designed to restrict the bandwidth consumed by control packets in ad hoc wireless networks by eliminating the periodic table-update messages that are required in the table-driven approach.
The Internet is a public network, based on known network protocols such as TCP/IP, which specifications are widely and published. Hence, a third party (‘attacker’) may hijack, intercept, alter, tamper with and interpret any clear text packets transferred over the Internet rendering the transport of messages across the Internet non-secured. Methods of attacking data carried over the Internet include using network packet sniffers, IP spoofing, man-in-the-middle attacks and more. As such, there is a need to secure sensitive or confidential information transported over the Internet, such as bank account details and credit card numbers exchanged during a commercial transaction, medical records, criminal records, vehicle driver information, loan applications, stock trading, voter registration and other sensitive information carried over the Internet. Commonly, such data is not carried as clear text but is rather encrypted, so that the data is transferred over the Internet as transformed (or scrambled) data forming unreadable formats (typically by using a mathematical algorithm).
Encryption based mechanisms are commonly end-to-end processes involving only the sender and the receiver, where the sender encrypts the plain text message by transforming it using an algorithm, making it unreadable to anyone, except the receiver which possesses special knowledge. The data is then sent to the receiver over a network, and when received the special knowledge enables the receiver to reverse the process (decrypt) to make the information readable as in the original message. The encryption process commonly involves computing resources such as processing power, storage space and requires time for executing the encryption/decryption algorithm, which may delay the delivery of the message.
Transport Layer Security (TLS) and its predecessor Secure Sockets Layer (SSL) are non-limiting examples of end-to-end cryptographic protocols, providing secured communication above the OSI Transport Layer, using keyed message authentication code and symmetric cryptography. In client/server applications, the TLS client and server negotiate a stateful connection by using a handshake procedure, during which various parameters are agreed upon, allowing a communication in a way designed to prevent eavesdropping and tampering. The TLS 1.2 is defined in RFC 5246, and several versions of the protocol are in widespread use in applications such as web browsing, electronic mail, Internet faxing, instant messaging and Voice-over-IP (VoIP). In application design, TLS is usually implemented on top of any of the Transport Layer protocols, encapsulating the application-specific protocols such as HTTP, FTP, SMTP, NNTP, and XMPP. Historically, it has been used primarily with reliable transport protocols such as the Transmission Control Protocol (TCP). However, it has also been implemented with datagram-oriented transport protocols, such as the User Datagram Protocol (UDP) and the Datagram Congestion Control Protocol (DCCP), a usage which has been standardized independently using the term Datagram Transport Layer Security (DTLS). A prominent use of TLS is for securing World Wide Web traffic carried by HTTP to form HTTPS. Notable applications are electronic commerce and asset management. Increasingly, the Simple Mail Transfer Protocol (SMTP) is also protected by TLS (RFC 3207). These applications use public key certificates to verify the identity of endpoints. Another Layer 4 (Transport Layer) and upper layers encryption-based communication protocols include SSH (Secure Shell) and SSL (Secure Socket Layer).
Layer 3 (Network Layer) and lower layer encryption based protocols include IPsec, L2TP (Layer 2 Tunneling Protocol) over IPsec, and Ethernet over IPsec. The IPsec is a protocol suite for securing IP communication by encrypting and authenticating each IP packet of a communication session. The IPsec standard is currently based on RFC 4301 and RFC 4309, and was originally described in RFCs 1825-1829, which are now obsolete, and uses the Security Parameter Index (SPI, as per RFC 2401) as an identification tag added to the header while using IPsec for tunneling the IP traffic. An IPsec overview is provided in Cisco Systems, Inc. document entitled: “An Introduction to IP Security (IPSec) Encryption”, which is incorporated in its entirety for all purposes as if fully set forth herein.
Two common approaches to cryptography are found in U.S. Pat. No. 3,962,539 to Ehrsam et al., entitled “Product Block Cipher System for Data Security”, and in U.S. Pat. No. 4,405,829 to Rivest et al., entitled “Cryptographic Communications System and Method”, which are incorporated in their entirety for all purposes as if fully set forth herein. The Ehrsam patent discloses what is commonly known as the Data Encryption Standard (DES), while the Rivest patent discloses what is commonly known as the RSA algorithm (which stands for Rivest, Shamir and Adleman who first publicly described it), which is widely used in electronic commerce protocols. The RSA involves using a public key and a private key. DES is based upon secret-key cryptography, also referred to as symmetric cryptography, and relies upon a 56-bit key for encryption. In this form of cryptography, the sender and receiver of cipher text both possess identical secret keys, which are, in an ideal world, completely unique and unknown to the world outside of the sender and receiver. By encoding plain text into cipher text using the secret key, the sender may send the cipher text to the receiver using any available public or otherwise insecure communication system. The receiver, having received the cipher text, decrypts it using the secret key to arrive at the plain text.
An example of a method for Internet security is disclosed in U.S. Pat. No. 6,070,154 to Tavor et al. entitled: “Internet Credit Card Security” which is incorporated in its entirety for all purposes as if fully set forth herein. The patent discloses a method for transmitting credit card numbers in a secured manner via the Internet, wherein the security is provided by transmitting the credit card number in a plurality of different transmissions, each transmission containing part of the credit card number. Another method is disclosed in U.S. Pat. No. 6,012,144 to Pickett entitled: “Transaction Security Method and Apparatus” which is incorporated in its entirety for all purposes as if fully set forth herein, suggesting to use two or more non-secured networks to ensure transaction security. U.S. Pat. No. 7,774,592 to Ishikawa et al. entitled: “Encryption Communication Method”, which is incorporated in its entirety for all purposes as if fully set forth herein, discloses a secure communication system, which executes, on an open network to which many and unspecified nodes are connected, encryption-based communication between nodes belonging to a specific group.
There is a growing widespread use of the Internet for carrying multimedia, such as video and audio. Various audio services include Internet-radio stations and VoIP (Voice-over-IP). Video services over the Internet include video conferencing and IPTV (IP Television). In most cases, the multimedia service is a real-time (or near real-time) application, and thus sensitive to delays over the Internet. In particular, two-way services such a VoIP or other telephony services and video-conferencing are delay sensitive. In some cases, the delays induced by the encryption process, as well as the hardware/software costs associated with the encryption, render encryption as non-practical. Therefore, it is not easy to secure enough capacity of the Internet accessible by users to endure real-time communication applications such as Internet games, chatting, VoIP, MoIP (Multimedia-over-IP), etc. In this case, there may be a data loss, delay or severe jitter in the course of communication due to the property of an Internet protocol, thereby causing inappropriate real-time video communication. The following chapters of the publication number 1-587005-001-3 by Cisco Systems, Inc. (7/99) titled: “Internetworking Technologies Handbook”, relate to multimedia carried over the Internet, and are all incorporated in their entirety for all purposes as if fully set forth herein: Chapter 18: “Multiservice Access Technologies” (pages 18-1 to 18-10), and Chapter 19: “Voice/Data Integration Technologies” (pages 19-1 to 19-30).
VoIP systems in widespread use today fall into three groups: systems using the ITU-T H.323 protocol, systems using the SIP protocol, and systems that use proprietary protocols. H.323 is a standard for teleconferencing that was developed by the International Telecommunications Union (ITU). It supports full multimedia audio, video and data transmission between groups of two or more participants, and it is designed to support large networks. H.323 is network-independent: it can be used over networks using transport protocols other than TCP/IP. H.323 is still a very important protocol, but it has fallen out of use for consumer VoIP products due to the fact that it is difficult to make it work through firewalls that are designed to protect computers running many different applications. It is a system best suited to large organizations that possess the technical skills to overcome these problems.
SIP (for Session Initiation Protocol) is an Internet Engineering Task Force (IETF) standard signaling protocol for teleconferencing, telephony, presence and event notification and instant messaging. It provides a mechanism for setting up and managing connections, but not for transporting the audio or video data. It is probably now the most widely used protocol for managing Internet telephony Like the IETF protocols, SIP is defined in a number of RFCs, principally RFC 3261. A SIP-based VoIP implementation may send the encoded voice data over the network in a number of ways. Most implementations use Real-time Transport Protocol (RTP), which is defined in RFC 3550. Both SIP and RTP are implemented on UDP, which, as a connectionless protocol, can cause difficulties with certain types of routers and firewalls. Usable SIP phones therefore also need to use STUN (for Simple Traversal of UDP over NAT), a protocol defined in RFC 3489 that allows a client behind a NAT router to find out its external IP address and the type of NAT device.
Onion routing (OR) is a technique for anonymous communication over the Internet or any other computer network. Messages are repeatedly encrypted and then sent through several network nodes called onion routers. Each onion router removes a layer of encryption to uncover routing instructions, and sends the message to the next router where this is repeated. This prevents these intermediary nodes from knowing the origin, destination, and contents of the message. To prevent an adversary from eavesdropping on message content, messages are encrypted between routers. The advantage of onion routing (and mix cascades in general) is that it is not necessary to trust each cooperating router; if one or more routers are compromised, anonymous communication can still be achieved. This is because each router in an OR network accepts messages, re-encrypts them, and transmits to another onion router. The idea of onion routing (OR) is to protect the privacy of the sender and the recipient of a message, while also providing protection for message content as it traverses a network. Onion routing accomplishes this according to the principle of Chaum mix cascades: messages travel from source to destination via a sequence of proxies (“onion routers”), which re-route messages in an unpredictable path.
Routing onions are data structures used to create paths through which many messages can be transmitted. To create an onion, the router at the head of a transmission selects a number of onion routers at random and generates a message for each one, providing it with symmetric keys for decrypting messages, and instructing it which router will be next in the path. Each of these messages, and the messages intended for subsequent routers, is encrypted with the corresponding router's public key. This provides a layered structure, in which it is necessary to decrypt all outer layers of the onion in order to reach an inner layer. Onion routing is described in U.S. Pat. No. 6,266,704 to Reed et al. entitled: “Onion Routing Network for Securely Moving data through Communication Networks”, which is incorporated in its entirety for all purposes as if fully set forth herein. Other prior art publications relating to onion routing are the publications “Probabilistic Analysis of Onion Routing in a Black-box Model [Extended Abstract]” presented in WPES'07: Proceedings of the 2007 ACM Workshop on Privacy in Electronic Society, “A Model of Onion Routing with Provable Anonymity” presented in Proceedings of Financial Cryptography and Data Security '07, and “A Model of Onion Routing with Provable Anonymity”, presented in the Financial Cryptography and Data Security, 11th International Conference, all by Feigenbaum J., Johnson J. and Syverson P., publications “Improving Efficiency and Simplicity of Tor circuit establishment and hidden services”, Proceedings of the 2007 Privacy Enhancing Technologies Symposium, Springer-Verlag, LNCS 4776, publication “Untraceable electronic mail, return addresses, and digital pseudonyms” by Chaum D., in Communications of the ACM 24(2), February 1981, and “Valet Services: Improving Hidden Servers with a Personal Touch”, Proceedings of the 2006 Privacy Enhancing Technologies Workshop, Springer-Verlag, LNCS 4285, both by Overlier L., Syverson P., publications “Making Anonymous Communication”, Generation 2 Onion Routing briefing slides, Center for High Assurance Computer Systems, naval Research Laboratory, Presented at the National Science Foundation, Jun. 8, 2004 by Syverson P., publications “Onion Routing Access Configurations, “DISCEX 2000: Proceedings of the DARPA Information Survivability Conference and Exposition”, Volume I Hilton Head, S.C., IEEE CS Press, January 2000, “Onion Routing for Anonymous and Private Internet Connections,” Communications of the ACM, vol. 42, num. 2, February 1999, and “Anonymous Connections and Onion Routing,” IEEE Journal on Selected Areas in Communication Special Issue on Copyright and Privacy Protection, 1998, all by Syverson P., Reed M. G., Goldschlag M., publication “Towards an Analysis of Onion Routing Security, and “Workshop on Design Issues in Anonymity and Unobservability Berkeley, Calif., July 2000 by Syverson P., Tsudik G., Reed M. G., and Landwehr C, which are incorporated in their entirety for all purposes as if fully set forth herein.
‘Tor’ is an anonymizing network based on the principles of ‘onion routing’, and involves a system which selects a randomly chosen route for each connection, via the routers present in the Tor network. The last server appears herein as an ‘exit node’ and sends the data to the final recipient after leaving the Tor cloud. At this point, it is no longer possible for an observer constantly watching the ‘exit node’ to determine who the sender of the message was. This concept and its components are known from the ‘Tor’ project in http://www.torproject.org. The Tor network concept is described in U.S. Patent Application Publication 2010/0002882 to Rieger et al., in the publication “Tor: The Second-Generation Onion Router”, in Proceedings of the 13th USENIX Security Symposium August 2004, by Dingledine R., Mathewson N., Syverson P., in publication “Tor Protocol specification” by Dingledine R. and Mathewson N., in publication “Tor Directory Protocol, Version 3”, and publication “TC: A Tor Control Protocol” downloaded from the Tor web-site, which are incorporated in their entirety for all purposes as if fully set forth herein.
In computer architecture, such as the in the hosts or the servers above, a bus is a subsystem commonly consisting of a conductor, or group of conductors, that are used for carrying signals, data or power, and typically serves as a common connection between the circuits, devices or other components. A bus can be used for transferring data between components within a computer system, between computers or between a computer and peripheral devices. Many physical or logical arrangements may be used to implement a bus, such as parallel (wherein each data word is carried in parallel on multiple electrical conductors or wires), serial (such as bit-serial connections), or a combination of both, and the bus may be wired in various topologies such as multi-drop (electrical parallel) or daisy-chain. Further, a bus may be implemented as a communication network employing hubs or switches. A bus may be internal, commonly implemented as a passive back-plane or motherboard conductors, or external, the latter is commonly a cable, and may use passive or active circuitry. A bus may further carry a power signal (commonly low-voltage DC power signal, e.g., 3.3 Volts DC (VDC), 5 VDC, 12 VDC and 48 VDC). In a parallel bus, the number of lines or wires, or the number of bits carried in parallel, is referred to as the bus width.
A non-limiting schematic example of a computer system 160 employing memory-mapped I/O (Input/Output) scheme is shown in FIG. 16. A processor 163 (which may serve as a CPU—Central Processing Unit) is connected to a memory 162 and I/O circuitry 161 via bus 164. The bus 164 comprises three buses, an address bus 166, a data 167 and control bus 165. The address bus 166 carries the address specified by the processor 163, relating to the physical or virtual location in the memory 162, or physical or virtual specific I/O component, while the value to be read or written is sent on the data bus 167. The control bus 165 carries control information between the processor 163 and other devices, such as commands from the processor 163 or signals that report to the processor 163 the status of various devices such as memory 162 and I/O 161, and also for controlling and supporting the address bus 166 and the data bus 167. As a non-limiting example, one line of the control bus may be used to indicate whether the CPU 163 is currently reading from, or writing to, the memory 162 (R/W line). The address bus 166 and the data bus 167 may be carried separately over dedicated conductors (non-multiplexed bus), or alternatively may be carried over the same conductors using time-multiplexing.
A schematic non-limiting example of detailed coupling of a memory component 171 to address bus 166, data bus 167 and control bus 165 is shown in sub-system 170 shown in FIG. 17. The memory 171 is capable of storing 256 bytes (256*8), and thus addressable by 8 address lines A7 (MSB—Most Significant Bit), A6, A5, A4, A3, A2, A1 and A0 (LSB—Least Significant Bit), connected via A7 line 176a, A6 line 176b, A5 line 176c, A4 line 176d, A3 line 176e, A2 line 176f, A1 line 176g and A0 line 176h, collectively referred to as address bus 176 carrying the address word. The processor specifies an address over the address bus 166, and the address bus 176 may be coupled to receive the address from the address bus 166 via an address logic circuit 174. The address logic circuit 174 may be a simple buffer or line-driver, or may be a latch or register that are commonly used in a multiplexed bus environment. Similarly, data values to be written to, or read from, the memory 171 are coupled to or from the data 167 via data logic 175, may be a simple bi-directional buffer or line-driver, or may be a bi-directional latch or register which are commonly used in a multiplexed bus environment. The 8 bits data word is designated as D7 (MSB), D6, D5, D4, D3, D2, D1 and D0 (LSB), connected via D7 line 177a, D6 line 177b, D5 line 177c, D4 line 177d, D3 line 177e, D2 line 177f, D1 line 177g and D0 line 177h, collectively referred to as data bus 177 carrying the address word. The control block 172 connects to the control bus 165 and may also be coupled to the address bus 166 and the data bus 167, and produce the signal R/W 173 which connects to the memory 171 to indicate a Write cycle (R/W=Logic ‘0’) or a Read cycle (R/W=Logic ‘1’). A non-limiting example of a processor may be 80186 or 80188 available from Intel Corporation located at Santa-Clara, Calif., USA. The 80186 and its detailed memory connections are described in the manual “80186/80188 High-Integration 16-Bit Microprocessors” by Intel Corporation, which is incorporated in its entirety for all purposes as if fully set forth herein. Another non-limiting example of a processor may be MC68360 available from Motorola Inc. located at. Schaumburg, Ill., USA. The MC68360 and its detailed memory connections are described in the manual “MC68360 Quad Integrated Communications Controller—User's Manual” by Motorola, Inc., which is incorporated in its entirety for all purposes as if fully set forth herein. While exampled above regarding an address bus having 8-bit width, other widths of address buses are commonly used, such as the 16-bit, 32-bit and 64-bit. Similarly, while exampled above regarding a data bus having 8-bit width, other widths of data buses are commonly used, such as 16-bit, 32-bit and 64-bit width.
There is a requirement for protecting data stored in a memory from authorized use. The terms “memory” and “storage” are used interchangeably herein and refer to any physical component that can retain or store information (that can be later retrieved) such as digital data on a temporary or permanent basis, typically for use in a computer or other digital electronic device. A memory can store computer programs or any other sequence of instructions, or data such as files, text, numbers, audio and video, as well as any other form of information represented as a string of bits or bytes. The physical means of storing information may be electrostatic, ferroelectric, magnetic, acoustic, optical, chemical, electronic, electrical, or mechanical. A memory may be in a form of Integrated Circuit (IC, a.k.a. chip or microchip). Alternatively or in addition, the memory may be in the form of a packaged functional assembly of electronic components (module). Such module may be based on a PCB (Printed Circuit Board) such as PC Card according to Personal Computer Memory Card International Association (PCMCIA) PCMCIA 2.0 standard, or a Single In-line Memory Module (SIMM) (or DIMM) which is standardized under the JEDEC JESD-21C standard. Further, a memory may be in the form of a separately rigidly enclosed box such as hard-disk drive.
Semiconductor memory may be based on Silicon-On-Insulator (SOI) technology, where a layered silicon-insulator-silicon substrate is used in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS, and are less common). SOI-Based memories include Twin Transistor RAM (TTRAM) and Zero-capacitor RAM (Z-RAM).
A memory may be a volatile memory, where a continuous power is required to maintain the stored information such as RAM (Random Access Memory), including DRAM (Dynamic RAM) or SRAM (Static RAM), or alternatively be a non-volatile memory which does not require a maintained power supply, such as Flash memory, EPROM, EEPROM and ROM (Read-Only Memory). Volatile memories are commonly used where long-term storage is required, while non-volatile memories are more suitable where fast memory access is required. Volatile memory may be dynamic, where the stored information is required to be periodically refreshed (such as re-read and then re-written) such as DRAM, or alternatively may be static, where there is no need to refresh as long as power is applied, such as RAM. In some cases, a small battery is connected to a low-power consuming volatile memory, allowing its use as a non-volatile memory.
A memory may be read/write (or mutable storage) memory where data may be overwritten more than once and typically at any time, such as RAM and Hard Disk Drive (HDD). Alternatively, a memory may be an immutable storage where the information is retained after being written once. Once written, the information can only be read and typically cannot be modified, sometimes referred to as Write Once Read Many (WORM). The data may be written at the time of manufacture of the memory, such as mask-programmable ROM (Read Only Memory) where he data is written into the memory a part of the IC fabrication, CD-ROM (CD—Compact Disc) and DVD-ROM (DVD—Digital Versatile Disk, or Digital Video Disk). Alternately, the data may be once written to the “write once storage” at some point after manufacture, such as Programmable Read-Only Memory (PROM) or CD-R (Compact Disc-Recordable).
A memory may be accessed using “random access” scheme where any location in the storage can be accessed at any moment in typically the same time, such as RAM, ROM or most semiconductor-based memories. Alternatively, a memory may be of “sequential access” type, where the pieces of information are gathered or stored in a serial order, and therefore the time to access a particular piece of information or a particular address depends upon which piece of information was last accessed, such as magnetic tape based storage. Common memory devices are location-addressable, where each individually accessible unit of data in storage is selected using its numerical memory address. Alternatively, a memory may be file-addressable, where the information is divided into files of variable length, and a file is selected by using a directory or file name (typically a human readable name), or may be content-addressable, where each accessible unit of information is selected based on the basis of (or part of) the stored content. File addressability and content addressability commonly involves additional software (firmware) or hardware or both.
Various storage technologies are used for the medium (or media) that actually holds the data in the memory. Commonly in use are semiconductor, magnetic, and optical mediums. Semiconductor based medium is based on transistors, capacitors or other electronic components in an IC, such as RAM, ROM and Solid-State Drives (SSDs). A currently popular non-volatile semiconductor technology is based on a flash memory, and can be electrically erased and reprogrammed. The flash memory is based on NOR or NAND based single-level cells (SLC) or multi-level cells (MLC), made from floating-gate transistors. Non-limiting examples of applications of flash memory include personal and laptop computers, PDAs, digital audio players (MP3 players), digital cameras, mobile phones, synthesizers, video games consoles, scientific instrumentation, industrial robotics and medical electronics. The magnetic storage uses different types of magnetization on a magnetically or ferromagnetic coated surface as a medium for storing the information. The information is accessed by read/write heads or other transducers. Non-limiting examples of magnetic-based memory are Floppy-disk, magnetic tape data storage and HDD. In optical storage typically an optical disc is used, that stores information in deformities on the surface of a circular disc, and the information is read by illuminating the surface with a laser diode and observing the reflection. The deformities may be permanent (read only media), formed once (write once media) or reversible (recordable or read/write media). Non-limiting examples of read-only storage, commonly used for mass distribution of digital information such as music, audio, video or computer programs, include CD-ROM, BD-ROM (BD—Blu-ray Disc) and DVD-ROM. Non-limiting examples of write once storage are CD-R, DVD-R, DVD+R and BD-R, and non-limiting examples of recordable storage are CD-RW (Compact Disc-ReWritable), DVD-RW, DVD+RW, DVD-RAM and BD-RE (Blu-ray Disc Recordable Erasable). Another non-limiting example is magneto-optical disc storage, where the magnetic state of a ferromagnetic surface stores the information, which can be read optically. 3D optical data storage is an optical data storage, in which information can be recorded and/or read, with three-dimensional resolution.
A storage medium may be removable, designed to be easily removed from, and easily installed or inserted into, the computer by a person, typically without the need for any tool and without the need to power off the computer or the associated drive. Such capability allows for archiving, for transporting data between computers, and for buying and selling software. The medium may be read using a reader or player that reads the data from the medium, or may be written by a burner or writer, or may be used for writing and reading by a writer/reader commonly referred to as a drive. Commonly in the case of magnetic or optical based mediums, the medium has the form factor of a disk, which is typically a round plate on which the data is encoded, respectively known as magnetic disc and optical disk. The machine that is associated with reading data from and writing data onto a disk is known as a disk drive. Disk drives may be internal (integrated within the computer enclosure) or may be external (housed in a separate box that connects to the computer). Floppy disks, that can be read from or written on by a floppy drive, are a non-limiting example of removable magnetic storage medium, and CD-RW (Compact Disc-ReWritable) is a non-limiting example of a removable optical disk. A non-volatile removable semiconductor based storage medium is commonly in use and is referred to as a memory card. A memory card is a small storage device, commonly based on flash memory, and can be read by a suitable card reader.
A memory may be accessed via a parallel connection or bus (wherein each data word is carried in parallel on multiple electrical conductors or wires), such as PATA, PCMCIA or EISA, or via serial bus (such as bit-serial connections) such as USB or Ethernet based on IEEE802.3 standard, or a combination of both. The connection may further be wired in various topologies such as multi-drop (electrical parallel), point-to-point, or daisy-chain. A memory may be powered via a dedicated port or connector, or may be powered via a power signal carried over the bus, such as SATA or USB.
A memory may be provided according to a standard, defining its form factor (such as its physical size and shape) and electrical connections (such as power and data interface). A standard-based memory may be easily inserted to, or removed from, a suitable corresponding slot (a.k.a. expansion slots) of a computer or other digital device. In one non-limiting example, a memory card using a PC Card form factor according to PCMCIA 2.0 (or JEIDA 4.1) is used, suitable for mounting into a corresponding PCMCIA-compatible slot, supporting 16 or 32-bit width interface, and connected via 68 pins connectors. Similarly, CardBus according to PCMCIA 5.0 may be used. In one non-limiting example, the memory is in the form of SD (Secure Digital) Card, based on standard by SD Card Association (SDA), which is commonly used in many small portable devices such as digital video camcorders, digital cameras, audio players and mobile phones. Other types of memory cards may be equally used, such as CompactFlash (CF), MiniSD card, MicroSD Card, and xD-Picture Card.
In another non-limiting example, a memory may be provided as a USB drive (such as USB Flash drive), which is a portable enclosed card that plugs into a computer USB port and communicates with a USB host. Such flash-based memory drives are commonly referred to as “thumb drives”, “jump drives” and “memory sticks”. Such USB mass storage devices and others are described in “Chapter 1: Mass Storage basics”, downloaded 10/2011 from: http://www.1vr.com/files/usb_mass_storage_chapter_1.pdf, which is incorporated in its entirety for all purposes as if fully set forth herein. In another non-limiting example, the memory is designed to fit into a drive bay in a computer enclosure. Commonly such drive bays are standard-sized, and used to store disk drives. The drives may be usually secured with screws or using a tool-less fasteners. A current popular standard is the 3.5 inches (3.5″) bays, which dimensions are specified in SFF standard specifications SFF-8300 and SFF-8301, which were incorporated into the EIA (Electronic Industries Association) standard EIA-470.
Traditionally, computer related storage was categorized to main memory, secondary and tertiary storages, having different latency (access time), capacity, and size. The main memory (or primary memory or internal memory) referred to the memory that was directly accessible by the CPU, and typically stored the program to be executed by the processor. The secondary storage (or external memory or auxiliary storage) referred to a memory which was not directly accessible to the CPU and thus required input/output channels, commonly offering larger storage capacity than the main memory. The tertiary storage involved mass storage media, commonly associated with a dismount removable media, used for archiving rarely accessed information. The latency of accessing a particular location is typically nanoseconds for primary storage, milliseconds for secondary storage, and seconds for tertiary storage. The capacity of a memory is commonly featured in bytes (B), where the prefix ‘K’ is used to denote kilo=210=10241=1024, the prefix ‘M’ is used to denote mega=220=10242=1,048,576, the prefix ‘G’ is used to denote giga=230=10243=1,073,741,824, and the prefix ‘T’ is used to denote tera=240=10244=1,099,511,627,776.
A memory may be Direct-attached Storage (DAS), where the memory is directly connected to a host, computer, server, or workstation, commonly without a network in between. Common examples involve a number of hard disk drives (HDD) connected to a processor or a computer through a Host Bus Adapter (HBA). Commonly serial and point-to-point connections are used, such as SATA, eSATA, SCSI, SAS and Fibre Channel. Alternatively, a memory can be part of a Network-attached Storage (NAS), wherein a self-contained file level storage (typically arranged as a server) is connected to a network, providing data sharing to other devices (such as heterogeneous clients), commonly via a network device such as a hub, switch or router. NAS is specialized for its task by its hardware, software, or both, and thus provides faster data access, easier administration, and simple configuration. NAS is typically associated with a LAN, and commonly provides an Ethernet interface based on IEEE802.3 standard may be used such as 10/100BaseT, 1000BaseT/TX (gigabit Ethernet), 10 gigabit Ethernet (10 GE or 10 GbE or 10 GigE per IEEE Std 802.3ae-2002as standard), 40 Gigabit Ethernet (40 GbE), or 100 Gigabit Ethernet (100 GbE as per Ethernet standard IEEE P802.3ba). In another alternative, a memory may be part of a Storage Area Network (SAN), which is a high-speed (commonly dedicated) network (or sub-network) for sharing storage devices, such as disk arrays, tape libraries and optical jukeboxes. The SAN typically allows multiple computers or servers to access multiple storage devices using a network such as WAN or LAN. SAN often utilizes a Fibre Channel fabric topology, commonly made up of a number of Fibre Channel switches.
Molecular memory uses molecular species as the data storage element. The molecular component can be described as a molecular switch, and may perform this function by any of several mechanisms, including charge storage, photochromism, or changes in capacitance. In a molecular memory device, each individual molecule contains a bit of data, leading to massive data capacity.
Blu-ray Disc (official abbreviation BD) is an optical disc storage medium designed to supersede the DVD format, where blue laser is used to read the disc, allowing information to be stored at a greater density than is possible with the longer-wavelength red laser used for DVDs. The disc diameter is 120 mm and the disc thickness is 1.2 mm of plastic optical disc, the same size as DVDs and CDs. Blu-ray Discs contain 25 GB (23.31 GiB) per layer, with dual layer discs (50 GB) being the norm for feature-length video discs. Triple layer discs (100 GB) and quadruple layers (128 GB) are available for BD-XL Blu-ray re-writer drives. The Blu-ray technology and its uses are described in the White Paper “Blu-ray Disc Format, 4. Key Technologies”, by Blu-ray Disc Founders, August 2004, in the brochure “Blu-ray Technology—DISCover the infinite storage media”, by DISC Archiving Systems B.V., 2010, and in Whitepaper “Sustainable Archival Storage—“The Benefits of Optical Archiving””, by DISC Archiving Systems B.V., downloaded from www.disc-group.com, which are all incorporated in their entirety for all purposes as if fully set forth herein.
Today, Hard Disk Drives (HDD) are used as secondary storage in general purpose computers, such as desktop personal computers and laptops. An HDD is a non-volatile, random access digital data storage device, featuring rotating rigid platters on a motor-driven spindle within a protective enclosure. The enclosure may be internal to the computer system enclosure or external. Data is magnetically read from, and written to, the platter by read/write heads that floats on a film or air above the platters. The HDDs are typically interfaced using high-speed interfaces, commonly of serial type. Common HDDs structure, characteristics, operation, form factors and interfacing is described in “Hard-Disk Basics” compiled from PCGUIDE.COM by Mehedi Hasan, which is incorporated in its entirety for all purposes as if fully set forth herein. Most SSDs include a controller that incorporates the electronics that bridge the NAND memory components to the host computer. The controller is an embedded processor that executes firmware-level code and is one of the most important factors of SSD performance. Functions performed by the controller include Error correction (ECC), Wear leveling, Bad block mapping, Read scrubbing and read disturb management, Read and write caching, and Garbage collection. Information about SSD technology, marketing and applications are provided in Martin B., Dell “DELL Solid State Disk (SSD) Drive—Storage Solutions for Select Poweredge Server”, May 2009, in Janukowicz J., Reisel D., White-Paper “MLC Solid State Drives: Accelerating the Adoption of SSDs”, IDC #213730, September 2008, and in Dufrasne B., Blum K, Dubberke U., IBM Corp. Redbooks Redpaper “DS8000: Introducing Solid State Drives”, 2009, which are all incorporated in their entirety for all purposes as if fully set forth herein.
The connection of peripherals and memories to a processor may be via a bus. A communication link (such as Ethernet, or any other LAN, PAN or WAN communication link) may also be regarded as bus herein. A bus may be an internal bus (a.k.a. local bus), primarily designed to connect a processor or CPU to peripherals inside a computer system enclosure, such as connecting components over the motherboard or backplane. Alternatively, a bus may be an external bus, primarily intended for connecting the processor or the motherboard to devices and peripherals external to the computer system enclosure. Some buses may be doubly used as internal or as external buses. A bus may be of parallel type, where each word (address or data) is carried in parallel over multiple electrical conductors or wires; or alternatively, may be bit-serial, where bits are carried sequentially, such as one bit at a time. A bus may support multiple serial links or lanes, aggregated or bonded for higher bit-rate transport. Non-limiting examples of internal parallel buses include ISA (Industry Standard architecture); EISA (Extended ISA); NuBus (IEEE 1196); PATA—Parallel ATA (Advanced Technology Attachment) variants such as IDE, EIDE, ATAPI, SBus (IEEE 1496), VESA Local Bus (VLB), PCI and PC/104 variants (PC/104, PC/104 Plus, PC/104 Express). Non-limiting examples of internal serial buses include PCIe (PCI Express), Serial ATA (SATA), SMBus, and Serial Peripheral Bus (SPI) bus. Non-limiting examples of external parallel buses include HIPPI (HIgh Performance Parallel Interface), IEEE-1284 (‘Centronix’), IEEE-488 (a.k.a. GPIB—General Purpose Interface Bus) and PC Card/PCMCIA. Non-limiting examples of external serial buses include USB (Universal Serial Bus), eSATA and IEEE 1394 (a.k.a. FireWire). Non-limiting examples of buses that can be internal or external are Futurebus, InfiniBand, SCSI (Small Computer System Interface), and SAS (Serial Attached SCSI). The bus medium may be based on electrical conductors, commonly copper wires based cable (may be arranged as twisted-pairs) or a fiber-optic cable. The bus topology may use point-to-point, multi-drop (electrical parallel) and daisy-chain, and may further be based on hubs or switches. A point-to-point bus may be full-duplex, providing simultaneous, two-way transmission (and sometimes independent) in both directions, or alternatively a bus may be half-duplex, where the transmission can be in either direction, but only in one direction at a time. Buses are further commonly characterized by their throughput (data bit-rate), signaling rate, medium length, connectors and medium types, latency, scalability, quality-of-service, devices per connection or channel, and supported bus-width. A configuration of a bus for a specific environment may be automatic (hardware or software based, or both), or may involve user or installer activities such as software settings or jumpers. Recent buses are self-repairable, where spare connection (net) is provided which is used in the event of malfunction in a connection. Some buses support hot-plugging (sometimes known as hot swapping), where a connection or a replacement can be made, without significant interruption to the system or without the need to shut-off any power. A well-known example of this functionality is the Universal Serial Bus (USB) that allows users to add or remove peripheral components such as a mouse, keyboard, or printer. A bus may be defined to carry a power signal, either in separate dedicated cable (using separate and dedicated connectors), or commonly over the same cable carrying the digital data (using the same connector). Typically dedicated wires in the cable are used for carrying a low-level DC power levels, such as 3.3 VDC, 5 VDC, 12 VDC and any combination thereof. A bus may support master/slave configuration, where one connected node is typically a bus master (e.g., the processor or the processor-side), and other nodes (or node) are bus slaves. A slave may not connect or transmit to the bus until given permission by the bus master. A bus timing, strobing, synchronization, or clocking information may be carried as a separate signal (e.g. clock signal) over a dedicated channel, such as separate and dedicated wired in a cable, or alternatively may use embedded clocking (a.k.a. self-clocking), where the timing information is encoded with the data signal, commonly used in line codes such as Manchester code, where the clock information occurs at the transition points. Any bus or connection herein may use proprietary specifications, or preferably be similar to, based on, substantially or fully compliant with an industry standard (or any variant thereof) such as those referred to as PCI Express, SAS, SATA, SCSI, PATA, InfiniBand, USB, PCI, PCI-X, AGP, Thunderbolt, IEEE 1394, FireWire and Fibre Channel.
Fibre Channel, or FC, is a gigabit-speed network technology primarily used for storage networking, and has recently become the standard connection type for storage area networks (SAN) in enterprise storage. Fibre Channel is standardized in the T11 Technical Committee of the InterNational Committee for Information Technology Standards (INCITS), an American National Standards Institute (ANSI) accredited standards committee. Fibre Channel signaling can run on both twisted pair copper wire and fiber-optic cables. Fibre Channel Protocol (FCP) is a transport protocol (similar to TCP used in IP networks) that predominantly transports SCSI commands over Fibre Channel networks. There are three major Fibre Channel topologies, describing how a number of ports are connected together: Point-to-Point (FC-P2P), where two devices are connected directly to each other; Arbitrated loop (FC-AL) where all devices are in a loop or ring (similar to token ring networking); and Switched fabric (FC-SW), where devices or loops of devices are connected to Fibre Channel switches (similar conceptually to modern Ethernet implementations). Some Fibre Channel devices support SFP transceiver, mainly with LC fiber connector, while some 1GFC devices used GBIC transceiver, mainly with SC fiber connector. Fibre Channel is further described in “Fibre Channel Solutions Guide” by FCIA—Fibre Channel Industry Association (www.fibrechannel.org, September 2010), “Technology Brief—Fibre Channel Basics”, by Apple Computer, Inc. (May 2006), and Weimer T. of Unylogix, “Fibre Channel Fundamentals” (available for download from the Internet 10/2011), which are all incorporated in their entirety for all purposes as if fully set forth herein.
InfiniBand is a switched fabric communications link used in high-performance computing and enterprise data centers. Its features include high throughput, low latency, quality of service and failover, and it is designed to be scalable. InfiniBand offers point-to-point bidirectional serial links intended for the connection of processors with high-speed peripherals such as disks. On top of the point-to-point capabilities, InfiniBand also offers multicast operations as well. It supports several signaling rates and links can be bonded together for additional throughput. The SDR serial connection's signaling rate is 2.5 gigabit per second (Gbit/s) in each direction per connection. DDR is 5 Gbit/s and QDR is 10 Gbit/s. FDR is 14.0625 Gbit/s and EDR is 25.78125 Gbit/s per lane. Lanes can be aggregated in units of 4 or 12, called 4× or 12×. A 12×QDR link therefore carries 120 Gbit/s raw, or 96 Gbit/s of useful data. As of 2009, most systems use a 4× aggregate, implying a 10 Gbit/s (SDR), 20 Gbit/s (DDR) or 40 Gbit/s (QDR) connections. InfiniBand uses a switched fabric topology, as opposed to a hierarchical switched network like traditional Ethernet architectures. Most of the network topologies are Fat-Tree (Clos), mesh or 3D-Torus. The InfiniBand technology is further described in the White Paper “Introduction to InfiniBand™” Mellanox technologies Inc., Document Number 2003WP Rev. 1.90, in the document by Grun P. of InfiniBand™ Trade Association: “Introduction to InfiniBand™ for End Users”, 2010, and in the White Paper “An Introduction to InfiniBand—Bringing I/O up to speed” Rev. Number: v1.1, by JNI Corporation, Jan. 25, 2002, which are all incorporated in their entirety for all purposes as if fully set forth herein.
Serial ATA (SATA or Serial Advanced Technology Attachment) is a computer bus interface for connecting host bus adapters to mass storage devices such as hard disk drives and optical drives. Serial ATA industry compatibility specifications originate from The Serial ATA International Organization (a.k.a. SATA-IO, serialata.org), and the specification defines three distinct protocol layers: physical, link, and transport. Serial ATA was designed to replace the older parallel ATA (PATA) standard (often called by the old name IDE), offering several advantages over the older interface: reduced cable size and cost (7 conductors instead of 40), native hot swapping, faster data transfer through higher signaling rates, and more efficient transfer through an (optional) I/O queuing protocol. SATA host-adapters and devices communicate via a high-speed serial cable over two pairs of conductors. In contrast, parallel ATA (PATA) used a 16-bit wide data bus with many additional support and control signals, all operating at much lower frequency. To ensure backward compatibility with legacy ATA software and applications, SATA uses the same basic ATA and ATAPI command-set as legacy ATA devices. Advanced Host Controller Interface (AHCI) is an open host controller interface published and used by Intel, which has become a de facto standard. It allows the use of the advanced features of SATA such as hotplugging and native command queuing (NCQ). If AHCI is not enabled by the motherboard and chipset, SATA controllers typically operate in “IDE emulation” mode, which does not allow features of devices to be accessed if the ATA/IDE standard does not support them. The SATA standard defines a data cable with seven conductors (3 grounds and 4 active data lines in two pairs) and 8 mm wide wafer connectors on each end. SATA cables can have lengths up to 1 meter (3.3 ft), and connect one motherboard socket to one hard drive. The SATA standard specifies a power connector that differs from the decades-old four-pin Molex connector found on pre-SATA devices Like the data cable, it is wafer-based, but its wider 15-pin shape prevents accidental mis-identification and forced insertion of the wrong connector type. Standardized in 2004, eSATA (the ‘e’ standing for external) provides a variant of SATA meant for external connectivity. While it has revised electrical requirements and the connectors and cables are not identical with SATA, the protocol and logical signaling are compatible on the (internal) SATA level. SATA uses a point-to-point architecture. The physical connection between a controller and a storage device is not shared among other controllers and storage devices. SATA defines multipliers, which allows a single SATA controller to drive multiple storage devices. The multiplier performs the function of a hub; the controller and each storage device are connected to the hub. The SATA bus, protocol and applications are further described in “Serial ATA technology, Technology Brief, 4th edition”, by Hewlett-Packard Development Company, L.P., TC1108815, October 2011, in white paper “External Serial ATA”, by Silicon Image, Inc., September 2004, in Krotov I. Redpaper: “IBM System x Server Disk Drive Interface Technology”, IBM Corp. Document REDP-4791-00, Oct. 10, 2011, “Serial ATA Advanced Host Controller Interface (AHCI)”, Revision 1.0, downloaded from Intel website, October 2011, and white-paper “Serial ATA—A comparison with Ultra ATA Technology”, downloaded from www.seagate.com on 10/2011, which are all incorporated in their entirety for all purposes as if fully set forth herein.
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards. PCIe has numerous improvements over the aforementioned bus standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance-scaling for bus devices, a more detailed error detection and reporting mechanism, and native hot plug functionality. More recent revisions of the PCIe standard support hardware I/O virtualization. The PCIe electrical interface is also used in a variety of other standards, most notably ExpressCard, a laptop expansion card interface. Format specifications are maintained and developed by the PCI-SIG (PCI Special Interest Group), a group of more than 900 companies that also maintain the Conventional PCI specifications. PCIe 3.0 is the latest standard for expansion cards that is available on mainstream personal computers. Conceptually, the PCIe bus is like a high-speed serial replacement of the older PCI/PCI-X bus an interconnect bus using shared address/data lines. A key difference between a PCIe bus and the older PCI is the bus topology. PCI uses a shared parallel bus architecture, where the PCI host and all devices share a common set of address/data/control lines. In contrast, PCIe is based on point-to-point topology, with separate serial links connecting every device to the root complex (host). Due to its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to 1 master at a time, in a single direction. A PCIe bus link supports full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints. In terms of bus protocol, PCIe communication is encapsulated in packets. The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCIe port (described later). Radical differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors (and thus, new motherboards and new adapter boards); PCI slots and PCIe slots are not interchangeable. The PCIe link between 2 devices can consist of anywhere from 1 to 32 lanes. In a multi-lane link, the packet data is striped across lanes, and peak data-throughput scales with the overall link width. The lane count is automatically negotiated during device initialization, and can be restricted by either endpoint. For example, a single-lane PCIe (×1) card can be inserted into a multi-lane slot (×4, ×8, etc.), and the initialization cycle auto-negotiates the highest mutually supported lane count. The link can dynamically down-configure the link to use fewer lanes, thus providing some measure of failure tolerance in the presence of bad or unreliable lanes. The PCIe standard defines slots and connectors for multiple widths: ×1, ×4, ×8, ×16, and ×32. As a point of reference, a PCI-X (133 MHz 64 bit) device and PCIe device at 4-lanes (×4), Gen1 speed have roughly the same peak transfer rate in a single-direction: 1064 MB/sec. The PCIe bus has the potential to perform better than the PCI-X bus in cases where multiple devices are transferring data communicating simultaneously, or if communication with the PCIe peripheral is bidirectional. A lane is commonly composed of a transmit pair and a receive pair, each of differential lines. Each lane is composed of 4 wires or signal paths, meaning conceptually, each lane is a full-duplex byte stream, transporting data packets in 8-bit ‘byte’ format, between the endpoints of a link, in both directions simultaneously. Physical PCIe slots may contain from one to thirty-two lanes, in powers of two (1, 2, 4, 8, 16 and 32). Lane counts are written with an × prefix (e.g., ×16 represents a sixteen-lane card or slot), with ×16 being the largest size in common use. A PCIe card fits into a slot of its physical size or larger (maximum ×16), but may not fit into a smaller PCIe slot (×16 in an ×8 slot). Some slots use open-ended sockets to permit physically longer cards and negotiate the best available electrical connection. The number of lanes actually connected to a slot may also be less than the number supported by the physical slot size. A non-limiting example is a ×8 slot that actually only runs at ×1. These slots allow any ×1, ×2, ×4 or ×8 cards, though only running at ×1 speed. This type of socket is called a ×8 (×1 mode) slot, meaning that it physically accepts up to ×8 cards, but only runs at ×1 speed. The advantage is that it can accommodate a larger range of PCIe cards without requiring motherboard hardware to support the full transfer rate. This keeps the design and implementation costs down. The PCIe uses double-sided edge-connector, and power is provided over the same connection. PCI Express Mini Card (also known as Mini PCI Express, Mini PCIe, and Mini PCI-E) is a replacement for the Mini PCI form factor, based on PCI Express. PCI Express Mini Cards are 30×50.95 mm. There is a 52 pin edge connector, consisting of two staggered rows on a 0.8 mm pitch. Each row has 8 contacts, a gap equivalent to 4 contacts, then a further 18 contacts. A half-length card is also specified 30×26.8 mm. Cards have a thickness of 1.0 mm (excluding components). AdvancedTCA is a PCIe variant providing a complement to CompactPCI for larger applications; supports serial based backplane topologies. AMC: a complement to the AdvancedTCA specification; supports processor and I/O modules on ATCA boards (×1, ×2, ×4 or ×8 PCIe). It has the connector bracket reversed so it cannot fit in a normal PCI Express socket, but is pin compatible and may be inserted if the bracket is removed. FeaturePak is a tiny expansion card format (43×65 mm) for embedded and small form factor applications; it implements two ×1 PCIe links on a high-density connector along with USB, I2C, and up to 100 points of I/O. Thunderbolt is a variant from Intel that combines DisplayPort and PCIe protocols in a form factor compatible with Mini DisplayPort. The PCIe is further described in the tutorial “PCI Express—An Overview of the PCI Express Standard”, National Instruments, Published Aug. 13, 2009, in the White Paper “Creating a PCI Express™ Interconnect”, Intel Corporation, Downloaded 10/2011, in “PHY Interface for the PCI Express™ Architecture”, Version 2.00, Intel Corporation 2007, and in Cooper S., One Stop Systems, Presentation “Utilizing PCI Express Technology”, Downloaded 10/2011, which are all incorporated in their entirety for all purposes as if fully set forth herein.
Serial Attached SCSI (SAS) is a computer bus based on a point-to-point serial protocol that replaces the parallel SCSI bus technology and uses the standard SCSI command set. SAS offers backwards-compatibility with second-generation SATA drives. SATA 3 Gbit/s drives may be connected to SAS backplanes, but SAS drives may not be connected to SATA backplanes. The T10 technical committee of the International Committee for Information Technology Standards (INCITS) develops and maintains the SAS protocol; the SCSI Trade Association (SCSITA) promotes the technology. SASA is based on full-duplex with link aggregation (4-ports wide at 24 Gbit/s) over 10 meters external cable, and may connect to 255 device port expanders. At the physical layer, the SAS standard defines the connectors and voltage levels. The physical characteristics of the SAS wiring and signaling are compatible with and have loosely tracked that of SATA up to the present 6 Gbit/s rate, although SAS defines more rigorous physical signaling specifications as well as a wider allowable differential voltage swing intended to support longer cabling. While SAS-1.0/SAS-1.1 adopted the physical signaling characteristics of SATA at the 1.5 Gbit/s and 3 Gbit/s rates, SAS-2.0 development of a 6 Gbit/s physical rate led the development of an equivalent SATA speed. According to the SCSI Trade Association, 12 Gbit/s is slated to follow 6 Gbit/s in a future SAS-3.0 specification.
A typical Serial Attached SCSI system consists of an initiator, a target, a Service Delivery Subsystem and expanders: An Initiator is a device that originates device-service and task-management requests for processing by a target device and receives responses for the same requests from other target devices. Initiators may be provided as an on-board component on the motherboard (as is the case with many server-oriented motherboards) or as an add-on host bus adapter. A Target is a device containing logical units and target ports that receives device service and task management requests for processing and sends responses for the same requests to initiator devices. A target device could be a hard disk or a disk array system. A Service Delivery Subsystem is the part of an I/O system that transmits information between an initiator and a target. Typically, cables connecting an initiator and target with or without expanders and backplanes constitute a service delivery subsystem. Expanders are devices that form part of a service delivery subsystem and facilitate communication between SAS devices. Expanders facilitate the connection of multiple SAS End devices to a single initiator port. An initiator may connect directly to a target via one or more PHYs. Nearline SAS or NL-SAS drives are enterprise SATA drives with a SAS interface, head, media, and rotational speed of traditional enterprise-class SATA drives with the fully capable SAS interface typical for classic SAS drives.
The components known as Serial Attached SCSI Expanders (SAS Expanders) facilitate communication between large numbers of SAS devices. Expanders contain two or more external expander-ports. Each expander device contains at least one SAS Management Protocol target port for management and may contain SAS devices itself. For example, an expander may include a Serial SCSI Protocol target port for access to a peripheral device. An expander is not necessary to interface a SAS initiator and target but allows a single initiator to communicate with more SAS/SATA targets. Edge expanders can do direct table routing and subtractive routing. A fanout expander can connect up to 255 sets of edge expanders, known as an edge expander device set, allowing for even more SAS devices to be addressed. The subtractive routing port of each edge expanders will be connected to the PHYs of a fanout expander. The SAS is further described in White Paper “serial Attached SCSI and Serial Compatibility”, Intel Corporation Doc. 0103/OC/EW/PP/1K-254402-001, 2002, in the Product Manual “Serial Attached SCSI (SAS) Interface Manual”, Publication number: 100293071, Rev. B, Seagate Technology LLC, May 2006, and in Technology Brief, 4th edition, “Serial Attached SCSI technologies and architectures”, Hewlett-Packard Development Company, L.P., TC0000772, August 2011, which are all incorporated in their entirety for all purposes as if fully set forth herein.
USB (Universal Serial Bus) is an industry standard developed in the mid-1990s that defines the cables, connectors and protocols used for connection, communication and power supply between computers and electronic devices. USB was designed to standardize the connection of computer peripherals, such as keyboards, pointing devices, digital cameras, printers, portable media players, disk drives and network adapters to personal computers, both to communicate and to supply electric power. It has become commonplace on other devices, such as smartphones, PDAs and video game consoles. USB has effectively replaced a variety of earlier interfaces, such as serial and parallel ports, as well as separate power chargers for portable devices. A USB system has an asymmetric design, consisting of a host, a multitude of downstream USB ports, and multiple peripheral devices connected in a tiered-star topology. Additional USB hubs may be included in the tiers, allowing branching into a tree structure with up to five tier levels. A USB host may have multiple host controllers and each host controller may provide one or more USB ports. Up to 127 devices, including the hub devices (if present), may be connected to a single host controller. USB devices are linked in series through hubs. There always exists one hub known as the root hub, which is built into the host controller. A physical USB device may consist of several logical sub-devices that are referred to as device functions. A host assigns one and only one device address to a function.
USB device communication is based on pipes (logical channels). A pipe is a connection from the host controller to a logical entity, found on a device, and named an endpoint. Because pipes correspond 1-to-1 to endpoints, the terms are sometimes used interchangeably. A USB device can have up to 32 endpoints: 16 into the host controller and 16 out of the host controller. The USB standard reserves one endpoint of each type, leaving a theoretical maximum of 30 for normal use. USB devices seldom have this many endpoints. There are two types of pipes: stream and message pipes, depending on the type of data transfer: isochronous transfers, at some guaranteed data rate (often, but not necessarily, as fast as possible) but with possible data loss (e.g., real-time audio or video), interrupt transfers, relating devices that need guaranteed quick responses (bounded latency) (e.g., pointing devices and keyboards), bulk transfers, where large sporadic transfers using all remaining available bandwidth, but with no guarantees on bandwidth or latency (e.g., file transfers), and control transfers, typically used for short, simple commands to the device, and a status response, used, for example, by the bus control pipe number 0. Endpoints are grouped into interfaces and each interface is associated with a single device function. An exception to this is endpoint zero, which is used for device configuration and which is not associated with any interface. A single device function composed of independently controlled interfaces is called a composite device. A composite device only has a single device address because the host only assigns a device address to a function.
The USB 1.x and 2.0 specifications provide a 5 V supply on a single wire from which connected USB devices may draw power. The specification provides for no more than 5.25 V and no less than 4.75 V (5 V±5%) between the positive and negative bus power lines. For USB 3.0, the voltage supplied by low-powered hub ports is 4.45-5.25 V. A unit load is defined as 100 mA in USB 2.0, and 150 mA in USB 3.0. A device may draw a maximum of 5 unit loads (500 mA) from a port in USB 2.0; 6 (900 mA) in USB 3.0. There are two types of devices: low-power and high-power. A low-power device draws at most 1 unit load, with minimum operating voltage of 4.4 V in USB 2.0, and 4 V in USB 3.0. A high-power device draws the maximum number of unit loads permitted by the standard. Every device function initially as low-power, but the device may request high-power and will get it if the power is available on the providing bus. Some devices, such as high-speed external disk drives, require more than 500 mA of current and therefore cannot be powered from one USB 2.0 port. Such devices usually come with a Y-shaped cable that has two USB connectors to be plugged into a computer. With such a cable a device can draw power from two USB ports simultaneously. A bus-powered hub initializes itself at 1 unit load and transitions to maximum unit loads after it completes hub configuration. Any device connected to the hub will draw 1 unit load regardless of the current draw of devices connected to other ports of the hub (i.e. one device connected on a four-port hub will draw only 1 unit load despite the fact that more unit loads are being supplied to the hub). A self-powered hub will supply maximum supported unit loads to any device connected to it. In addition, the VBUS will present 1 unit load upstream for communication if parts of the hub are powered down.
USB supports the following signaling rates (the terms speed and bandwidth are used interchangeably, and “high-” is alternatively written as “hi-”). A low-speed rate of 1.5 Mbit/s (˜183 kB/s) is defined by USB 1.0. It is very similar to full-bandwidth operation except each bit takes 8 times as long to transmit. The full-speed rate of 12 Mbit/s (˜1.43 MB/s) is the basic USB data rate defined by USB 1.0. All USB hubs support full-bandwidth. A high-speed (USB 2.0) rate of 480 Mbit/s (˜57 MB/s) was introduced in 2001. All hi-speed devices are capable of falling back to full-bandwidth operation if necessary; i.e., they are backward compatible with USB 1.1. Connectors are identical for USB 2.0 and USB 1.x. A SuperSpeed (USB 3.0) provides a rate of 5.0 Gbit/s (˜596 MB/s). USB 3.0 connectors are generally backwards compatible, but include new wiring and full duplex operation. USB signals are transmitted on a twisted-pair data cable with 90Ω±15% characteristic impedance, labeled D+ and D−. Prior to USB 3.0, half-duplex differential signaling was used to reduce the effects of electromagnetic noise on longer lines. Transmitted signal levels are 0.0 to 0.3 volts for low and 2.8 to 3.6 volts for high in full-bandwidth and low-bandwidth modes, and −10 to 10 mV for low and 360 to 440 mV for high in hi-bandwidth mode. In FS mode, the cable wires are not terminated, but the HS mode has termination of 45Ω to ground, or 90Ω differential to match the data cable impedance, reducing interference due to signal reflections. USB 3.0 introduces two additional pairs of shielded twisted wire and new, mostly interoperable contacts in USB 3.0 cables, for them. They permit the higher data rate, and full duplex operation. The USB is further described in “Universal Serial Bus 3.0 Specification”, Revision 1.0, Jun. 6, 2011, downloaded from www.usb.org, and in Peacock C., “USB in a Nutshell”, 3rd Release, November 23, which are all incorporated in their entirety for all purposes as if fully set forth herein.
It is useful to protect users and data from unauthorized use or access. In one non-limiting example, user data or other confidential information may be left on disk drives removed from computers and storage systems, such as at systems end-of-life. For example, there is a legal requirement, according to the federal standard NIST 800-88: “Guidelines for Media Sanitization”, September 2006, for erasing (sanitizing) records, and as described in the Ponemon Institute document “Fourth Annual US Cost of Data Breach study”, January 2009, which are both incorporated in their entirety for all purposes as if fully set forth herein.
Such sanitization techniques use non destructive actions, such as deleting files and block erase (such by formatting or overwriting by external dedicated software, for example as required by DOD 5220), while other techniques use destructive means such as physical drive destruction and disk drive degaussing. When using physical drive destruction, disks removed from disk drives are broken up or ground into microscopic pieces. Similarly, degaussers may be used to erase magnetic data on disk drives, while creating high intensity magnetic fields that erase all magnetic recordings in a hard disk drive (or magnetic tape). A non-destructive means include in-drive encryption using an encryption key. Various sanitization requirements and schemes of disk drives, as well as limitations of the various schemes, are described in Hughes G., Coughlin T., “Tutorial on Disk Drive Data Sanitization” (September 2006), in Edelstein R., Converge Net Inc., “The Limitation of Software Based Hard Drive sanitization—The Myth of a Legacy Technology” (September 2007), in Edelstein R., Converge Net Inc., “Data Loss Prevention: Managing the Final Stage of the Data Life Cycle Model—A Perspective on Decommissioning Storage Technology” (May 2007), in Hughes G. F. and Commins D. M. of University of California, Coughlin T. of Coughling Associates, “Disposal of Disk and Tape Data by secure sanitization”, Co-published by the IEEE Computer and Reliability Societies (IEEE Security & Privacy pg. 29-34, July/August 2009), which are all incorporated in their entirety for all purposes as if fully set forth herein.
In consideration of the foregoing, it would be an advancement in the art to provide an improved networking or storage security method and system that is simple, secured, cost-effective, faithful, reliable, easy to use or sanitize, has a minimum part count, minimum hardware, and/or uses existing and available components, protocols, programs and applications for providing better security and additional functionalities, and provides a better user experience.